Single polarity programming of a pcram structure

ABSTRACT

A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of write pulses having the same polarity. The resistance variable memory element can be provided having at least one silver-selenide layer in between glass layers, the glass layers are a chalcogenide glass having a Ge x Se 100-x  composition.

FIELD OF THE INVENTION

[0001] The invention relates to the field of random access memory (RAM)devices formed using a resistance variable material, and in particularto a method and apparatus for writing a particular resistance state of achalcogenide glass memory element.

BACKGROUND OF THE INVENTION

[0002] Recently, resistance variable memory elements, which includeprogrammable conductor memory elements based on chalcongenide glasses,have been investigated for suitability as semi-volatile and non-volatilerandom access memory elements.

[0003] The mechanism by which the resistance of a chalcogenide glassmemory element is changed is not fully understood. In one theory, theconductively-doped dielectric material undergoes a structural change ata certain applied voltage. It is surmised that a conductive dendrite orfilament grows under influence of the applied voltage to extend betweenthe electrodes, effectively interconnecting the two electrodes andsetting the memory element to a low resistance state. The dendrite isthought to grow through the resistance variable material along a path ofleast resistance.

[0004] The low resistance state will remain intact for days or weeksafter the voltage potentials are removed. Such materials can be returnedto a high resistance state by applying a reverse voltage potentialbetween the electrodes, the reverse potential having at least the sameorder of magnitude as was used to write the element to the lowresistance state. Again, the highly resistive state is maintained oncethe voltage potential is removed. This way, such a device can function,for example, as a resistance variable memory element having tworesistance states, which can define two logic states.

[0005] As noted above, resistance variable materials of particularinterest include chalcogenide glasses doped with a conductive substancethat will disperse or migrate within the glass. A specific example isgermanium-selenide glass (Ge_(x)Se_(100-x)), doped with silver (Ag).Another example is a germanium-selenide glass (Ge_(x)Se_(100-x)) whichreceives silver ions through an adjacent silver-selenide (Ag₂Se) layer.

[0006] Known memory elements based on silver-containing chalcogenidematerials require that pulses of reverse polarity be applied to switchthe memory element between the different resistance states. Since it isoften inconvenient to supply a negative potential power source to amemory device, it would be desirable to have a resistance variablememory element which switches between resistance memory states usingdifferent levels of a positive voltage.

BRIEF SUMMARY OF THE INVENTION

[0007] In a first embodiment, the invention provides a resistancevariable memory element in which a metal, e.g., silver, containing layeris formed between two chalcogenide glass layers, the memory elementbeing switchable between two resistance states by application of writevoltage pulses of different levels but of the same polarity.

[0008] The metal-containing layer may be a layer of silver-selenideformed between the two chalcogenide glass layers.

[0009] According to a second embodiment, the invention provides a memoryelement including a plurality of alternating layers of chalcogenideglass and metal containing layers, whereby the layers start with a firstchlacogenide glass layer and end with a last chalcogenide glass layer,with the first chalcogenide glass layer contacting a first electrode andthe last chalcogenide glass layer contacting a second electrode. Theplurality of alternating layers of chalcogenide glass layers and metalcontaining layers are stacked between two electrodes. The metalcontaining layers preferably include a silver-chalcogenide, such assilver-selenide. The memory element of the second embodiment is alsoswitchable between two resistance states by application of write voltagepulses of different levels but of the same polarities.

[0010] These and other features and advantages of the invention will bebetter understood from the following detailed description, which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 illustrates a cross-sectional view of a simplified memoryelement and an accompanying read/write circuit in accordance with anexemplary embodiment of the present invention.

[0012]FIG. 2 illustrates a cross-sectional view of a simplified memoryelement in accordance with an alternative exemplary embodiment of thepresent invention.

[0013]FIG. 3 illustrates a cross-sectional view of a simplified memoryelement in accordance with another alternative exemplary embodiment ofthe present invention.

[0014]FIG. 4 illustrates a cross-sectional view of a simplified memoryelement in accordance with a further alternative exemplary embodiment ofthe present invention.

[0015]FIG. 5 is a graph illustrating write voltages and resistancestates of the memory elements of the present invention.

[0016]FIG. 6 illustrates a processor-based system having a memoryincluding memory elements in accordance with an exemplary embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In the following detailed description, reference is made tovarious specific embodiments of the invention. These embodiments aredescribed with sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that other embodimentsmay be employed, and that various structural, logical and electricalchanges may be made without departing from the spirit or scope of theinvention.

[0018] The term “substrate” used in the following description mayinclude any supporting structure including but not limited to asemiconductor substrate or a non-semiconductor substrate. Asemiconductor substrate should be understood to include silicon,silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures.

[0019] The term “silver” is intended to include not only elementalsilver, but silver with other trace metals or in various alloyedcombinations with other metals as known in the semiconductor industry,as long as such silver alloy is conductive, and as long as the physicaland electrical properties of the silver remain unchanged.

[0020] The term “silver-selenide” is intended to include various speciesof silver-selenide, including some species which have a slight excess(+x) or deficit (−x) of silver, for instance, Ag₂Se, Ag_(2+x)Se, andAg_(2−x)Se.

[0021] The term “chalcogenide glass” is intended to include glasses thatcontain an element from group VIA (or group 16) of the periodic table.Group VIA elements, also referred to as chalcogens, include sulfur (S),selenium (Se), tellurium (Te), polonium (Po), and oxygen (O).

[0022] The invention will now be explained with reference to FIG. 1,which illustrates an exemplary embodiments of a resistance variablememory element 2 in accordance with the invention. FIG. 1 depicts aportion of an insulating layer 12 formed over a substrate 10, forexample, a silicon substrate. It should be understood that theresistance variable memory element can be formed over a variety ofsubstrate materials and not just semiconductor substrates such assilicon. For example, the insulating layer 12 may be formed over aplastic substrate.

[0023] The insulating layer 12 may be formed by any known depositionmethods, such as sputtering by chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD) or physical vapor deposition (PVD). The insulatinglayer 12 may be formed of a conventional insulating oxide, such assilicon oxide (SiO₂), a silicon nitride (Si₃N₄), or a low dielectricconstant material, among many others.

[0024] A first electrode 14 is next formed over the insulating layer 12,as also illustrated in FIG. 1. The first electrode 14 may include anyconductive material, for example, tungsten, nickel, tantalum, aluminum,or platinum, among many others. A first dielectric layer 15 is nextformed over the first electrode 14. The first dielectric layer 15 mayinclude the same or different materials as those described above withreference to the insulating layer 12.

[0025] An opening extending to the first electrode 14 is formed in thefirst dielectric layer 15 by known methods in the art, for example, by aconventional patterning and etching process. A first chalcogenide glasslayer 17 is next formed over the first dielectric layer 15, to fill inthe opening.

[0026] According to a first exemplary embodiment of the invention, thefirst chalcogenide glass layer 17 is a germanium-selenide glass having aGe_(x)Se_(100-x) stoichiometry. The preferred stoichiometric range isbetween about Ge₁₈Se₈₂ to about Ge₄₃Se₅₇ and is more preferably aboutGe₄₀Se₆₀. The first chalcogenide glass layer 17 preferably has athickness from about 100 Å to about 1000 Å and is more preferably about150 A.

[0027] The first chalcogenide glass layer acts as a glass backbone forallowing a conductive, metal-containing layer, such as a silver-selenidelayer, to be directly deposited thereon. The use of a metal containinglayer, such as a silver-selenide layer, in contact with the chalcogenideglass layer makes it unnecessary to provide a metal (silver) dopedchalcogenide glass, which would require photodoping of the substratewith light radiation. It is possible, however, to also metal (silver)dope the chalcogenide glass layer, which is in contact with thesilver-selenide layer, as an optional variant.

[0028] The formation of the first chalcogenide glass layer 17, having astoichiometric composition in accordance with the invention, may beaccomplished by any suitable method. For instance, evaporation,co-sputtering germanium and selenium in the appropriate ratios,sputtering using a germanium-selenide target having the desiredstoichiometry, or chemical vapor deposition with stoichiometric amountsof GeH₄ and SeH₂ gases (or various compositions of these gases), whichresult in a germanium-selenide film of the desired stoichiometry areexamples of methods which may be used to form the first chalcogenideglass layer 17.

[0029] A first metal containing layer 18, preferably silver-selenide, isdeposited over the first chalcogenide glass layer 17. Any suitable metalcontaining layer may be used, including, for instance,silver-chalcogenide layers. Silver sulfide, silver oxide, and silvertelluride are all suitable silver-chalcogenides that may be used incombination with any suitable chalcogenide glass layer. A variety ofprocesses can be used to form the silver-selenide layer 18. Forinstance, physical vapor deposition techniques such as evaporativedeposition and sputtering may be used. Other processes such as chemicalvapor deposition, co-evaporation, or depositing a layer of seleniumabove a layer of silver to form silver-selenide can also be used.

[0030] The layers may be any suitable thickness. The thickness of thelayers depend upon the desired electrical switching characteristics. Thethickness of the layers is such that the metal containing layer isthicker than the first chalcogenide glass layer. The metal containinglayer is also thicker than a second chalcogenide glass layer, describedbelow. More preferably, the thicknesses of the layers are such that aratio of the silver-selenide layer thickness to the first chalcogenideglass layer thickness is between about 5:1 and about 1:1. In otherwords, the thickness of the silver-selenide layer is between about 1 toabout 5 times greater than the thickness of the first chalcogenide glasslayer. Even more preferably, the ratio is between about 3.1:1 and about2:1 silver-selenide layer thickness to first chalcogenide glass layerthickness.

[0031] A second chalcogenide glass layer 20 is formed over the firstsilver-selenide layer 18. The second chalcogenide glass layer allowsdeposition of silver above the silver-selenide layer since silver cannotbe directly deposited on silver-selenide. Also, it is believed that thesecond chalcogenide glass layer may prevent or regulate migration ofmetal, such as silver, from an electrode into the element. Accordingly,although the exact mechanism by which the second chalcogenide glasslayer may regulate or prevent metal migration is not clearly understood,the second chalcogenide glass layer may act as a silver diffusioncontrol layer. The second chalcogenide glass layer may, but need not,have the same stoichiometric composition as the first chalcogenide glasslayer, e.g., Ge_(x)Se_(100-x). Thus, the second chalcogenide glass layer20 may be of a different material, different stoichiometry, and/or morerigid than the first chalcogenide glass layer 17.

[0032] The thickness of the layers are such that the silver-selenidelayer 18 thickness is greater than the thickness of the secondchalcogenide glass layer 20. Preferably, a ratio of the silver-selenidelayer thickness to the second chalcogenide glass layer thickness isbetween about 5:1 and about 1:1. More preferably, the ratio of thesilver-selenide layer thickness to the thickness of the secondchalcogenide glass layer is between about 3.3:1 and about 2:1silver-selenide layer thickness to second chalcogenide glass layerthickness. The second chalcogenide glass layer 20 preferably has athickness between about 100 Å to about 1000 Å and is more preferably 150Å.

[0033] The formation of the second chalcogenide glass layer 20 may beaccomplished by any suitable method. For instance, chemical vapordeposition, evaporation, co-sputtering, or sputtering using a targethaving the desired stoichiometry, may be used.

[0034] A second conductive electrode material 22 is formed over thesecond chalcogenide glass layer 20. As with the first conductiveelectrode, the second conductive electrode material 22 may include anyelectrically conductive material, for example, tungsten, tantalum,titanium, or silver, among many others. Typically, the second conductiveelectrode material 22 includes silver. Thus, advantageously, the secondchalcogenide glass layer 20 may be chosen to considerably slow orprevent migration of electrically conductive metals, such as silver,through the resistance variable memory element 2.

[0035] One or more additional dielectric layers may be formed over thesecond electrode 22 and the first dielectric layer 15 to isolate theresistance variable memory element 2 from other structure fabricatedover the substrate 12. Conventional processing steps can then be carriedout to electrically couple the second electrode 22 to various circuitsof memory arrays.

[0036] A resistance variable memory element made of a PCRAM stackfabricated as described has been observed to switch to a low resistancestate upon application of a first positive write pulse across the upperand lower electrodes, and to switch to a high resistance state uponapplication of a second higher positive write pulse across theelectrodes. The pulses are applied by read/write circuit 24 as showndiagramatically in FIG. 1. The first and second positive write pulsesmay have a pulse width of less than or equal to 8 nanoseconds. The FIG.1 device switches to a low resistance state when the first write pulsehas a magnitude of in the range of about 500 mV to about 1 V. The lowresistance state is about 1 to 10 KΩ, and thus can be obtained with awrite pulse as low as about 500 mV. The device switches to a highresistance state when a second positive write pulse is applied having amagnitude of at least approximately 2.5 V, providing a high resistancestate in the Megohm range. Pulse widths longer than 8 nanoseconds can beused, and with the appropriate potential, can exceed 1 microsecond.Thus, the resistance variable memory element of the present invention isswitchable between two discrete resistance states, one lower and theother high, upon application of positive write voltage pulses.

[0037] Either resistance state can be read upon application of apositive voltage of less than 400 mV which will not erase the memory orcause a resistance change in the memory element. A destructive read isalso possible, whereby a negative or positive potential could be used toread the device and concomitantly perturb the state of the memory cellwhich then needs to be refreshed to its original memory state.

[0038] In accordance with a variation of the first embodiment of theinvention, one or more layers of a metal containing material, such assilver-selenide, may be deposited on the first chalcogenide glass layer17. Any number of silver-selenide layers may be used. Thus, an optionalsecond silver-selenide layer may be deposited on the firstsilver-selenide layer 18.

[0039] The thickness of the layers is such that the total thickness ofthe combined metal containing layers, e.g., silver-selenide layers, isgreater than or equal to the thickness of the first chalcogenide glasslayer. The total thickness of the combined metal containing layers isalso greater than the thickness of the second chalcogenide glass layer.It is preferred that the total thickness of the combined metalcontaining layers is between about 1 to about 5 times greater than thethickness of the first chalcogenide glass layer and accordingly betweenabout 1 to about 5 times greater than the thickness of the secondchalcogenide glass layer. It is even more preferred that the totalthickness of the combined metal containing layers is between about 2 toabout 3.3 times greater than the thicknesses of the first chalcogenideglass layer and the second chalcogenide glass layer.

[0040] In accordance, with yet another variation of the invention, thefirst chalcogenide glass layer may include one or more layers of achalcogenide glass material, such as germanium-selenide. The secondchalcogenide glass layer may also include one or more layers of achalcogenide glass material. Any suitable number of layers may be usedto include the first chalcogenide glass layer and/or the secondchalcogenide glass layer. It is to be understood, however, that thetotal thickness of the metal containing layer(s) should be thicker thanthe total thickness of the one or more layers of chalcogenide glass andadditionally the total thickness of the metal containing layer(s) shouldbe thicker than the total thickness of the one or more layers of thesecond chalcogenide glass layer. Preferably a ratio of the totalthickness of the metal containing layer(s) to the total thickness of theone or more layers of chalcogenide glass is between about 5:1 and about1:1. Also, a ratio of the total thickness of the metal containinglayer(s) to the total thickness of the one or more layers of the secondchalcogenide glass preferably is between about 5:1 and about 1:1. It iseven more preferred that the total thickness of the metal containinglayer(s) is between about 2 to about 3.3 times greater than the totalthicknesses of the combined one or more layers of chalcogenide glass andthe total thickness of the combined one or more layers of the secondchalcogenide glass.

[0041] In accordance with yet another variant of the invention, one ormore of the chalcogenide glass layers may also be doped with a dopant,such as a metal, preferably silver.

[0042] Referring now to FIG. 2, a second exemplary embodiment of thepresent invention is illustrated in which the stack of layers formedbetween the first and second electrodes may include alternating layersof chalcogenide glass and a metal containing layer such as asilver-selenide layer. As shown in FIG. 2, memory element 30 includes afirst chalcogenide glass layer 17 stacked atop a first electrode 14. Afirst silver-selenide layer 18 is stacked atop the first chalcogenideglass layer 17, a second chalcogenide glass layer 117 is stacked atopthe first silver-selenide layer 18, a second silver-selenide layer 118is stacked atop the second chalcogenide glass layer 117, and a thirdchalcogenide glass layer 217 is stacked atop the second silver-selenidelayer 118. The second conductive electrode 22 is formed over the fourthchalcogenide glass layer.

[0043] In accordance with the second embodiment, the stack includes atleast two metal containing layers and at least three chalcogenide glasslayers. However, it is to be understood that the stack may includenumerous alternating layers of chalcogenide glass and silver-selenide,so long as the alternating layers start with a first chalcogenide glasslayer and end with a last chalcogenide glass layer, with the firstchalcogenide glass layer contacting a first electrode and the lastchalcogenide glass layer contacting a second electrode. The thicknessand ratios of the alternating layers of silver-selenide and chalcogenideglass are the same as described above, in that the silver-selenidelayers are preferably thicker than connecting chalcogenide glass layers,in a ratio of between about 5:1 and about 1:1 silver-selenide layer toconnected chalcogenide glass layer, and more preferably between about3.3:1 and 2:1 silver-selenide layer to connected chalcogenide glasslayer.

[0044] In a variation of the second embodiment, one or more layers of ametal containing material, such as silver-selenide may be depositedbetween the chalcogenide glass layers. Any number of silver-selenidelayers may be used. In an additional variation, one or more Ag layer(s)can be included alternately with the silver-selenide layers.

[0045] In accordance, with yet another variation of the invention, eachof the chalcogenide glass layers may include one or more thinner layersof a chalcogenide glass material, such as germanium-selenide. Anysuitable number of layers may be used to include the chalcogenide glasslayers.

[0046] In yet another variation of the second embodiment of theinvention, one or more of the chalcogenide glass layers may also bedoped with a dopant such as a metal, preferably including silver.

[0047] Referring to FIG. 3, a simplified structure of a third exemplaryembodiment of a memory cell according to the present invention is shownin which a silver selenide layer 219 is formed on an electrode 214. Overthe silver selenide a layer of Ge₄₀Se₆₀ glass is disposed, on which anupper electrode 222 containing silver is provided. According to analternative version, silver selenide layer 218 is composed ofAg_(2+x)Se, in which case upper electrode 222 need not contain silverdue to the extra silver in layer 218.

[0048] Referring to FIG. 4, a fourth exemplary embodiment of the presentinvention is shown in which a silver-doped glass layer 317 is sandwichedbetween two electrodes 314 and 322. The silver-doped glass compositionGe_(x)Se_(100-x) needs to be in a stoichiometric range from Ge₁₈Se₈₂ toGe₄₃Se₅₇, and preferably Ge₂₅Se₇₅ doped with silver either fully orwithin 1-10% of the maximum amount of silver allowed to keep thematerial amorphous. The preferred silver-doped glass compositions aredescribed in commonly-assigned U.S. patent application Ser. No. ______(Attorney Docket No. M4065.0569), the disclosure of which isincorporated herein by reference.

[0049] Devices constructed according to the invention exhibit singlepolarity switching as illustrated in the graph of FIG. 5. Those having asilver-selenide layer disposed between two chalcogenide glass layers, inparticular, are switchable between two resistance states using positivevoltage pulses, and show improved memory retention and write/eraseperformance over conventional memory devices. These devices have alsoshown low resistance memory retention better than 1200 hours at roomtemperature.

[0050] Although the embodiments described above refer to the formationof only one resistance variable memory element 2, it must be understoodthat the invention contemplates the formation of any number of suchresistance variable memory elements, which can be fabricated in a memoryarray and operated with memory element access circuits.

[0051]FIG. 6 illustrates a typical processor-based system 40 whichincludes a memory circuit 42, for example a programmable conductor RAM,which employs resistance variable memory elements fabricated inaccordance with the invention. A processor system, such as a computersystem, generally includes a central processing unit (CPU) 44, such as amicroprocessor, a digital signal processor, or other programmabledigital logic devices, which communicates with an input/output (I/O)device 46 over a bus 48. The memory 42 communicates with the system overbus 48 typically through a memory controller.

[0052] In the case of a computer system, the processor system mayinclude peripheral devices such as a floppy disk drive 50 and a compactdisc (CD) ROM drive 52, which also communicate with CPU 44 over the bus48. Memory 42 is preferably constructed as an integrated circuit, whichincludes one or more resistance variable memory elements 2. If desired,the memory 42 may be combined with the processor, for example CPU 44, ina single integrated circuit.

[0053] The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A resistance variable memory elementcomprising: a structure comprising at least one chalcogenide glass layerformed between a pair of electrodes, said layer being constructed andarranged such that a resistance value of said memory element switchesfrom a higher to lower resistance state upon application of a positivevoltage in a first voltage range and from a lower to higher resistancestate upon application of a positive voltage in a second voltage range.2. The memory element of claim 1 wherein said at least one chalcogenideglass layer comprises a plurality of chalcogenide glass layers.
 3. Thememory element of claim 1 further comprising at least two chalcogenideglass layers arranged to sandwich at least one metal-containing layerbetween said two chalcogenide glass layers.
 4. The memory element ofclaim 1 wherein said at least one chalcogenide glass layer comprises amaterial having the formula Ge_(x)Se_(100-x) wherein x=18 to
 43. 5. Thememory element of claim 1 wherein said at least one chalcogenide glasslayer stoichiometry is about Ge₄₀Se₆₀.
 6. The memory element of claim 1wherein said at least one chalcogenide glass layer has a thicknessbetween about 100 Å and about 1000 Å.
 7. The memory element of claim 1wherein said at least one chalcogenide glass layer has a thickness ofabout 150 Å.
 8. The memory element of claim 1, further comprising atleast one metal containing layer disposed with said chalcogenide glasslayer between said electrodes.
 9. The memory element of claim 8 whereinsaid at least one metal containing layer comprises asilver-chalcogenide.
 10. The memory element of claim 8 wherein said atleast one metal containing layer comprises silver-selenide.
 11. Thememory element of claim 8 wherein said at least one metal containinglayer comprises silver-sulfide.
 12. The memory element of claim 8wherein said at least one metal containing layer comprises silver-oxide.13. The memory element of claim 8 wherein said at least one metalcontaining layer comprises silver-telluride.
 14. The memory element ofclaim 8 wherein said at least one metal containing layer has a firstthickness and said at least one chalcogenide glass layer has a secondthickness whereby a thickness ratio of said first thickness to saidsecond thickness is between about 5:1 to about 1:1.
 15. The memoryelement of claim 8 wherein said at least one metal containing layer hasa first thickness and said at least one chalcogenide glass layer has asecond thickness whereby a thickness ratio of said first thickness tosaid second thickness is between about 3.3:1 to about 2:1.
 16. Thememory element of claim 8 wherein said at least one metal containinglayer comprises a plurality of stacked metal containing layers.
 17. Thememory element of claim 16 where at least one of the stacked metalcontaining layers is a layer containing silver.
 18. The memory elementof claim 8 further comprising at least two metal containing layers andat least three chalcogenide glass layers arranged alternately.
 19. Thememory element of claim 1 wherein at least one of said at least onechalcogenide glass layers or said electrodes contains a metal dopant.20. The memory element of claim 19 wherein said metal dopant comprisessilver.
 21. A resistance variable memory device comprising: at least onememory element comprising at least one chalcogenide glass layer; and awrite circuit for applying a first positive voltage to said memoryelement to switch said memory element from a first resistance state to asecond resistance state and for applying a second positive voltage toswitch said memory element from said second resistance state to saidfirst resistance state.
 22. The memory device of claim 21 wherein saidat least one silver-chalcogenide layer comprises silver-selenide. 23.The memory device of claim 21 wherein said at least onesilver-chalcogenide layer comprises silver-sulfide.
 24. The memorydevice of claim 21 wherein said at least one silver-chalcogenide layercomprises silver-oxide.
 25. The memory device of claim 21 wherein saidat least one silver-chalcogenide layer comprises silver-telluride. 26.The memory device of claim 21 wherein said chalcogenide glass materialhas the formula Ge_(x)Se_(100-x), wherein x=18 to
 43. 27. The memorydevice of claim 26 wherein said chalcogenide glass materialstoichiometry is about Ge₄₀Se₆₀.
 28. The memory device of claim 21wherein at least one of said chalcogenide glass layers or saidelectrodes contains a metal dopant.
 29. The memory device of claim 28wherein said metal dopant comprises silver.
 30. The memory device ofclaim 21 comprising first and second silver-chalcogenide layers, whereinsaid first silver-chalcogenide layer has a first thickness, said secondchalcogenide glass layer has a second thickness, and a thickness ratioof said first thickness to said second thickness is between about 5:1 toabout 1:1.
 31. The memory device of claim 30 wherein saidsilver-chalcogenide layer has a first thickness, said secondchalcogenide glass layer has a second thickness, and a thickness ratioof said first thickness to said second thickness is between about 3.3:1to about 2:1.
 32. The memory element of claim 30, wherein at least oneof said first and second chalcogenide glass layers contains a metaldopant.
 33. The memory element of claim 32 wherein said metal dopantcomprises silver.
 34. A memory element comprising: a first electrode; afirst glass layer comprising Ge_(x)Se_(100-x), wherein x=18 to 43, saidfirst glass layer being electrically coupled with said first electrode;a first metal containing layer in contact with said first glass layer; asecond chalcogenide glass layer in contact with said first metalcontaining layer; and a second electrode electrically coupled with saidsecond chalcogenide glass layer, said memory element being constructedand arranged such that a resistance value of said memory elementswitches from a higher to lower resistance state upon application of apositive voltage in a first voltage range and from a lower to higherresistance state upon application of a positive voltage in an secondvoltage range.
 35. The memory element of claim 34 wherein x is about 40.36. The memory element of claim 34 wherein said first metal containinglayer comprises a silver-chalcogenide.
 37. The memory element of claim34 wherein said first metal containing layer comprises silver-selenide.38. The memory element of claim 34 wherein said first metal containinglayer comprises silver-sulfide.
 39. The memory element of claim 34wherein said first metal containing layer comprises silver-oxide. 40.The memory element of claim 34 wherein said first metal containing layercomprises silver-telluride.
 41. The memory element of claim 34 whereinsaid first metal containing layer comprises a plurality of metalcontaining layers in serial contact with each other.
 42. The memoryelement of claim 34 wherein at least one of said first glass layer andsaid second chalcogenide glass layer comprises a plurality of glasslayers in serial contact with each other.
 43. The memory element ofclaim 34 wherein at least one of said first and second chalcogenideglass layers contains a metal dopant.
 44. The memory element of claim 43wherein said metal dopant comprises silver.
 45. A chalcogenide glassstack comprising: a chalcogenide glass layer; at least one metalcontaining layer in contact with said chalcogenide glass layer; and asecond chalcogenide glass layer in contact with said metal containinglayer, said chalcogenide glass stack being constructed and arranged suchthat a resistance value of said memory element switches from a higher tolower resistance state upon application of a positive voltage in a firstvoltage range and from a lower to higher resistance state uponapplication of a positive voltage in an second voltage range differentfrom said first voltage range.
 46. The chalcogenide glass stack of claim45 further comprising a metal containing electrode in electricalcommunication with said second chalcogenide glass layer.
 47. Thechalcogenide glass stack of claim 45 wherein said at least one metalcontaining layer comprises a silver-chalcogenide.
 48. The chalcogenideglass stack of claim 45 wherein said at least one metal containing layercomprises silver-selenide.
 49. The chalcogenide glass stack of claim 45wherein said at least one metal containing layer comprisessilver-sulfide.
 50. The chalcogenide glass stack of claim 45 whereinsaid at least one metal containing layer comprises silver-oxide.
 51. Thechalcogenide glass stack of claim 45 wherein said at least one metalcontaining layer comprises silver-telluride.
 52. The chalcogenide glassstack of claim 45 wherein at least one or both of said chalcogenideglass layers contains a metal dopant.
 53. The chalcogenide glass stackof claim 52 wherein said metal dopant comprises silver.
 54. A memoryelement comprising: a first electrode; at least one first chalcogenideglass layer in electrical communication with said first electrode; atleast one first metal containing layer in contact with said at least onefirst chalcogenide glass layer; at least one second chalcogenide glasslayer in contact with said at least one first metal containing layer; atleast one second metal containing layer in contact with said at leastone second chalcogenide glass layer; at least one third chalcogenideglass layer in contact with said at least one second metal containinglayer; and a second electrode in electrical communication with said atleast one third chalcogenide glass layer, said memory element beingconstructed and arranged such that a resistance value of said memoryelement switches from a higher to lower resistance state uponapplication of a positive voltage in a first voltage range and from alower to higher resistance state upon application of a positive voltagein an second voltage range, said second voltage range being differentfrom the first voltage range.
 55. The memory element of claim 54 whereinsaid metal containing layers comprise one or more silver-selenidelayers.
 56. The memory element of claim 54 wherein one or more of saidchalcogenide glass layers comprise a plurality of chalcogenide glasslayers.
 57. The memory element of claim 54 wherein one or more of saidmetal containing layers comprises a plurality of metal containinglayers.
 58. The memory element of claim 54 wherein one or more of saidchalcogenide glass layers contains a metal dopant.
 59. The memoryelement of claim 58 wherein said metal dopant comprises silver.
 60. Amethod of forming a resistance variable memory element comprising thesteps of: forming a first electrode; forming a first chalcogenide glasslayer in contact with said first electrode; forming a first metalcontaining layer in contact with said first chalcogenide glass layer;and forming a second chalcogenide glass layer in electricalcommunication with said first metal containing layer; forming a secondmetal containing layer in contact with said first chalcogenide glasslayer; forming a third chalcogenide glass layer in contact with saidsecond metal containing layer; and forming a second electrode inelectrical communication with said third chalcogenide glass layer, saidmemory element being constructed and arranged such that a resistancevalue of said memory element switches from a higher to lower resistancestate upon application of a positive voltage in a first voltage rangeand from a lower to higher resistance state upon application of apositive voltage in an second voltage range.
 61. The method of claim 60wherein said chalcogenide glass layers comprise a material having theformula Ge_(x)Se_(100-x), wherein x is between about 18 to about
 43. 62.The method of claim 61 wherein said chalcogenide glass layers have astoichiometry of about Ge₄₀Se₆₀.
 63. The method of claim 60 wherein saidchalcogenide glass layers comprise a plurality of chalcogenide glasslayers.
 64. The method of claim 60 wherein said metal containing layerscomprise a plurality of metal containing layers.
 65. The method of claim60 wherein one or more of said chalcogenide glass layers contain a metaldopant.
 66. The method of claim 60 wherein one or more of said metalcontaining layers comprises silver-selenide.
 67. The method of claim 66wherein said metal dopant comprises silver.
 68. The method of claim 60wherein said metal containing layers have a thickness which is equal toor greater than the thickness of each of said chalcogenide glass layers.69. The method of claim 60 wherein each of said metal containing layershas a first thickness and each of said chalcogenide glass layers has asecond thickness whereby a thickness ratio of said first thickness tosaid second thickness is between about 5:1 to about 1:1.
 70. The methodof claim 69 further wherein said thickness ratio of said first thicknessto said second thickness is between about 3.3:1 to about 2:1.
 71. Amethod of forming a resistance variable memory element comprising:forming a first chalcogenide glass layer; forming a silver-selenidelayer in contact with said first glass layer; and forming a secondchalcogenide glass layer in contact with said silver-selenide layer,said memory element being constructed and arranged such that aresistance value of said memory element switches from a higher to lowerresistance state upon application of a first positive voltage and from alower to higher resistance state upon application of a positive voltagein an second voltage.
 72. The method of claim 71 wherein saidchalcogenide glass material has a stoichiometric composition of aboutGe₄₀Se₆₀.
 73. The method of claim 71 wherein at least one of said glasslayers contains a metal dopant.
 74. The method of claim 73 wherein saidmetal dopant comprises silver.
 75. The method of claim 71 furthercomprising the step of forming alternating layers of said chalcogenideglass material and said silver-selenide layer.
 76. The method of claim71 wherein said layer formed of said chalcogenide glass material furthercontains a metal dopant.
 77. The method of claim 76 wherein said metaldopant comprises silver.
 78. The method of claim 71 wherein said metalcontaining layer has a thickness which is equal to or greater than athickness of each of said first and second chalcogenide glass layers.79. The method of claim 71 wherein said metal containing layer comprisesa plurality of silver-selenide layers in serial contact with each other.80. A processor-based system, comprising: a processor; and a memorycircuit connected to said processor, said memory circuit including aresistance variable memory element comprising at least one metalcontaining layer, at least one chalcogenide glass layer, at least oneother chalcogenide glass layer, said metal containing layer beingprovided between said at least one chalcogenide glass layer and said atleast one other chalcogenide glass layer, said memory element beingconstructed and arranged such that a resistance value of said memoryelement switches from a higher to lower resistance state uponapplication of a first positive voltage and from a lower to higherresistance state upon application of a second positive voltage.
 81. Thesystem of claim 80 wherein said chalcogenide glass layer comprises amaterial having the formula Ge_(x)Se_(100-x), wherein x=18 to
 43. 82.The system of claim 81 wherein said chalcogenide glass layerstoichiometry is about Ge₄₀Se₆₀.
 83. The system of claim 80 wherein atleast one of said glass layers contains a metal dopant.
 84. The systemof claim 83 wherein said metal dopant comprises silver.
 85. The systemof claim 81 further comprising another metal containing layer in contactwith said at least one other chalcogenide glass layer and at least onethird chalcogenide glass layer in contact with said at least one secondmetal containing layer.
 86. The system of claim 81 wherein saidchalcogenide glass layers comprise a plurality of stacked chalcogenideglass layers.
 87. The system of claim 81 wherein said metal containinglayer comprises a plurality of stacked metal containing layers.
 88. Thesystem of claim 81 wherein at least one of said chalcogenide glasslayers comprises a metal dopant.
 89. The system of claim 81 wherein saidmetal containing layer comprises a silver-selenide layer.
 90. Aprocessor-based system, comprising: a processor; a memory circuitconnected to said processor, said memory circuit comprising a firstelectrode; at least one first chalcogenide glass layer in electricalcommunication with said first electrode; at least one first metalcontaining layer in contact with said at least one first chalcogenideglass layer; at least one second chalcogenide glass layer in contactwith said at least one first metal containing layer; at least one secondmetal containing layer in contact with said at least one secondchalcogenide glass layer; at least one third chalcogenide glass layer incontact with said at least one second metal containing layer; and asecond electrode in electrical communication with said at least onethird chalcogenide glass layer, said memory circuit being constructedand arranged such that a resistance value of said memory circuitswitches from a higher to lower resistance state upon application of afirst positive voltage and from a lower to higher resistance state uponapplication of a second positive voltage.
 91. The system of claim 90wherein said metal containing layers comprise one or moresilver-selenide layers.
 92. The system of claim 91 wherein one or moreof said chalcogenide glass layers comprise a plurality of chalcogenideglass layers.
 93. The system of claim 90 wherein one or more of saidmetal containing layers comprises a plurality of metal containinglayers.
 94. The system of claim 90 wherein one or more of saidchalcogenide glass layers contains a metal dopant.
 95. The system ofclaim 94 wherein said metal dopant comprises silver.
 96. A memoryelement comprising: a first electrode; a second electrode; and aplurality of chalcogenide glass layers and at least one metal containinglayers arranged between said first and second electrodes, whereby saidplurality of chalcogenide glass layers alternate with said at least onemetal containing layers, with one of said chalcogenide glass layersbeing in contact with said first electrode and another of saidchalcogenide glass layers being in contact with said second electrode,said memory element being constructed and arranged such that aresistance value of said memory element switches from a higher to lowerresistance state upon application of a positive voltage in a firstvoltage range and from a lower to higher resistance state uponapplication of a positive voltage in an second voltage range.
 97. Thememory element of claim 96 wherein said at least one metal containinglayers comprises one or more silver-selenide layers.
 98. The memoryelement of claim 96 wherein one or more of said plurality ofchalcogenide glass layers comprises a plurality of chalcogenide glasslayers.
 99. The memory element of claim 96 wherein one or more of saidat least one metal containing layers comprises a plurality of metalcontaining layers.
 100. The memory element of claim 96 wherein one ormore of said plurality of chalcogenide glass layers contains a metaldopant.
 101. The memory element of claim 100 wherein said metal dopantcomprises silver.
 102. A method of forming a resistance variable memoryelement comprising: forming a first electrode; forming a secondelectrode; and forming a plurality of chalcogenide glass layers and atleast one metal containing layer between said first and secondelectrodes, whereby said plurality of chalcogenide glass layersalternate with said at least one metal containing layers, with one ofsaid chalcogenide glass layers being in contact with said firstelectrode and another of said chalcogenide glass layers being in contactwith said second electrode, said layers being constructed and arrangedsuch that a resistance value of said memory element switches from ahigher to lower resistance state upon application of first a positivevoltage and from a lower to higher resistance state upon application ofa second positive voltage.
 103. The method of claim 102 wherein said atleast one metal containing layers comprises one or more silver-selenidelayers.
 104. The method of claim 102 wherein one or more of saidplurality of chalcogenide glass layers comprises a plurality ofchalcogenide glass layers.
 105. The method of claim 102 wherein one ormore of said at least one metal containing layers comprises a pluralityof metal containing layers.
 106. The method of claim 102 wherein one ormore of said plurality of chalcogenide glass layers contains a metaldopant.
 107. The method of claim 106 wherein said metal dopant comprisessilver.
 108. A resistance variable memory element comprising a PCRAMstack including amorphous semiconducting glass layers separated by alayer of silver-containing material, wherein the resistance variablememory element switches to a low resistance state upon application of afirst positive write pulse, and switches to a high resistance state byapplication of a second positive write pulse.
 109. A resistance variablememory element as in claim 108 wherein the amorphous semiconductingglass layers include chalcogenide glass.
 110. A resistance variablememory element as in claim 108 wherein a time duration of the first andsecond positive write pulses is less than about 8 nanoseconds.
 111. Aresistance variable memory element as in claim 108, wherein the firstpositive write pulse has a magnitude of between about 700 mV and about 1V.
 112. A resistance variable memory element as in claim 108 wherein thefirst positive write pulse has a magnitude of about 700 mV.
 113. Aresistance variable memory element as in claim 108 wherein the lowresistance state is about 10K Ohm.
 114. A resistance variable memoryelement as in claim 108 wherein the second positive write pulse has amagnitude of at least about 1.5 V.
 115. A resistance variable memoryelement as in claim 114 wherein the high resistance state is in theMegohm range.
 116. A resistance variable memory element comprising aPCRAM stack including amorphous semiconducting glass layers separated bya layer of silver-containing material, wherein a resistance value of theresistance variable memory element is switchable between two discretestates, one lower and the other high, upon application of respectivepositive voltages.